/*
 *  (c) 2015 fullhan.com
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE	0x40000000
#define CONFIG_NR_DRAM_BANKS		1
#define PHYS_SDRAM			CONFIG_SYS_SDRAM_BASE
#define PHYS_SDRAM_SIZE			0x04000000	/* 64 megs */
#define CONFIG_SYS_TEXT_BASE         0x40800000
#define CONFIG_SYS_INIT_SP_ADDR      (CONFIG_SYS_TEXT_BASE - 0x80000)
#define CONFIG_SYS_UBOOT_BASE        (CONFIG_SYS_TEXT_BASE)

#define CONFIG_SYS_LOAD_ADDR         (CONFIG_SYS_TEXT_BASE)
#define CONFIG_SYS_GBL_DATA_SIZE    128

#define CONFIG_SYS_DCACHE_OFF   1

/*
 * Hardware drivers
 */
#define FH_SERIAL_CONSOLE    0

/*#define CONFIG_FH_GMAC*/
#define GMAC_SPEED_SWITCH_PMU_REG_OFFSET	0x0c
#define GMAC_SPEED_SWITCH_BIT_POS      24
#define GMAC_SPEED_SWITCH_100M_VAL     0x01
#define FH_ENC28J60_SPIBUS_ID (1)
#define FH_ENC28J60_SPIBUS_CLK (12500000)



#define FH_TIMER1_CLOCK    (1000000)
#define FH_PTS_CLOCK       (1000000)
#define CONFIG_SYS_HZ_CLOCK (54000000) // arch timer

#define CONFIG_CMDLINE_TAG          1   /* enable passing of ATAGs  */
#define CONFIG_SETUP_MEMORY_TAGS    1
#define CONFIG_INITRD_TAG           1

/*
 * BOOTP options
 */
/*#define CONFIG_BOOTP_BOOTFILESIZE	1*/
/*#define CONFIG_BOOTP_BOOTPATH		1*/
/*#define CONFIG_BOOTP_GATEWAY		1*/
/*#define CONFIG_BOOTP_HOSTNAME		1*/

#define CONFIG_SYS_GBL_DATA_SIZE        128

/* spi */
#define CONFIG_HARD_SPI
#define SPI_32BIT_XFER_ENABLE
 #define SPI_QUAD_ENABLE
/*#define CONFIG_SPI1_ENABLE*/
#define SPI_MAX_BUS_NUM                (2)
#define SPI0_MAX_CS_NUM                (2)
#define SPI0_CS0                       (5)
#define SPI0_CS1                       (10)
#define SPI1_MAX_CS_NUM                (1)
#define SPI1_CS0                       (34)


/* SPIFlash */
#ifdef CONFIG_SPI_FLASH
# define CONFIG_SYS_SPI_WRITE_TOUT      (5*CONFIG_SYS_HZ)
# define CONFIG_ENV_SPI_BUS             (0)
# define CONFIG_ENV_SPI_CS              (0)
# define CONFIG_SF_DEFAULT_SPEED        (50000000) /* 50M */
# define CONFIG_ENV_SPI_MAX_HZ          (50000000) /* 50M */
# define CONFIG_ENV_SECT_SIZE           (0x1000)   /* Env sector Size 4k*/
# define CONFIG_ENV_OFFSET              (0x20000)
# define CONFIG_ENV_IS_IN_SPI_FLASH
#endif

/* spi nand flash */
#ifdef CONFIG_FH_SPI_NAND
# define CONFIG_SYS_SPI_WRITE_TOUT      (5*CONFIG_SYS_HZ)
# define CONFIG_SYS_MAX_NAND_DEVICE     (2)
# define CONFIG_ENV_OFFSET              (0x20000)
# define CONFIG_ENV_IS_IN_NAND
#endif

#define CONFIG_SYS_NAND_MAX_ECCPOS 128
#define CONFIG_SYS_NAND_MAX_OOBFREE 16

/* I2C RTC*/
/*#define CONFIG_FH_I2C*/
/*#define CONFIG_RTC_PCF8563*/
/*#define CONFIG_CMD_I2C*/
#ifndef CONFIG_SYS_I2C_RTC_ADDR
# define CONFIG_SYS_I2C_RTC_ADDR	0x51
#endif
#define CONFIG_SYS_I2C_SPEED		80000
/*
 * FH board specific data
 */

/* total memory available to uboot */
/*#define CONFIG_SYS_UBOOT_SIZE		(1024 * 1024)*/

/*#define CONFIG_RTC_FH*/
/* Ethernet */
/*#define CONFIG_MACB			1*/
/*#define CONFIG_PHY_RTL8201      1*/
/*#define CONFIG_PHY_TI83848    1*/
/*#define CONFIG_PHY_IP101G     1*/
/*#define CONFIG_PHY_MODE         "RMII"*/
#define CONFIG_NET_MULTI		1
#define CONFIG_NET_RETRY_COUNT		20
#define CONFIG_RESET_PHY_R		1
#define CONFIG_SYS_RX_ETH_BUFFER	32
#define CONFIG_MII
#define CONFIG_CMD_MII
#define ADJUST_LINK_PARTNER

#define CONFIG_IPADDR		10.81.81.81
#define CONFIG_SERVERIP		10.81.0.1
#define CONFIG_ETHADDR		10:20:30:40:50:60
#define CONFIG_ENV_OVERWRITE

/*
 * Boot option
 */

#define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
#define CONFIG_SYS_MEMTEST_END			(PHYS_SDRAM + 0x02000000)


/* bootstrap + u-boot + env + linux in dataflash on CS0 */
/*#define CONFIG_SYS_SPIFLASH_BASE_ADDR  	0*/
/* The following #defines are needed to get flash environment right */
#define CONFIG_SYS_MONITOR_BASE			( 0x20000)
#define CONFIG_ENV_ADDR					(CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE					0x20000 	/* Total Size of Environment Sector 64k */
#define FH_BOOTCMD_OFFSET			(0x8000)

#if TFTP_BOOT
#define CONFIG_BOOTCOMMAND	"tftp 0x40007fc0 uImage; bootm"
#else
#define CONFIG_BOOTCOMMAND	"sf probe 0; sf read 0x40007fc0 0x90000 0x300000; bootm"
#endif
#define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
				"root=/dev/ram0 "			\
				"mem=48M "

#define CONFIG_BAUDRATE		115200
#define CONFIG_SYS_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }

/*wdt*/
#define CONFIG_HW_WATCHDOG

#define CONFIG_SYS_NO_FLASH

#ifdef CONFIG_SELFTEST_CMD
#define CONFIG_CMD_UPGRADE
#define CONFIG_CMD_PRINT_PTS
/*cpu test case*/
#define CONFIG_CMD_CPU_TEST
/*ddr test case*/
#define CONFIG_CMD_DDR_FREQ_TEST
#endif

/*#define CONFIG_CMD_REFCOUNT*/

/*MMC*/
#define __LITTLE_ENDIAN                         1
#define CONFIG_GENERIC_MMC
#define EMMC_ENV_OFFSET      0x20000
#define CONFIG_CMD_MMC
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 1

#define CONFIG_SUPPORT_EMMC_BOOT
#define FH_MMC_SDC0
#define FH_MMC_1BIT
/*#define CONFIG_MMC_TRACE*/
#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_VFAT
#define CONFIG_FS_FAT
#define CONFIG_FAT_WRITE

#define SD0_POWER_CONTROL_GPIO                  5
#define CONFIG_SYS_MAXARGS              32
#define CONFIG_SYS_MAX_FLASH_BANKS       0
#define CONFIG_SYS_CBSIZE               256
#define CONFIG_SYS_MALLOC_LEN           ROUND(6 * CONFIG_ENV_SIZE + 128*1024, 0x1000)

/* mmc options default using: SDC0,4BIT*/
/* #define CONFIG_MMC_SDC1 */
/*#define CONFIG_MMC_1BIT*/
/*#define CONFIG_FH_DMA*/


/* version string, parser, etc */
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP

#ifdef CONFIG_FH_AES
#define CRYPTO_AES_ECB_SUPPORT
#define CRYPTO_AES_CBC_SUPPORT
#endif

#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE

#ifdef CONFIG_USB_XHCI_HCD
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS		2
#endif

#endif
